1. Field of the Invention
The present invention relates to a pulse width discriminating circuit, and more specifically to a pulse width discriminating circuit capable of decoding an input signal which has a variable period and which has been pulse-modulated.
2. Description of Related Art
Referring to FIG. 1, there is shown a block diagram of a conventional pulse width discriminating circuit.
The pulse width discriminating circuit shown in FIG. 1 includes an input terminal 7 receiving an external signal, an edge detecting circuit 5 receiving an input signal 13 supplied from the input terminal 7 and for outputting an edge detecting signal 14 when a rising edge of the input signal 13 is detected, and a counter 1 initialized by the edge detection signal 14 and for counting up a count clock f 8. The shown pulse width discriminating circuit also includes a capture register (called a "CPT register" hereinafter) 2 for storing a count value 9 of the counter 2 in response to the edge detecting signal 14, a compare register (called a "CRO register" hereinafter) 3 for designating a tinting where a level of the input signal 13 should be detected, a comparator 4 for comparing the count value 9 of the counter 1 with a stored value 10 of the CRO register 3 and for generating a coincidence signal 11 when the count value 9 of the counter 1 becomes coincident with a stored value 10 of the CRO register 3, and a latch 6 responding to the coincidence signal 11 to latch the level of the input signal 13 and to output the latched level as a latched data 12. Furthermore, the shown pulse width discriminating circuit includes an arithmetic operation circuit 100 configured to receive a stored value 101 in the CPT register 2 and to multiply the received stored value 101 by a value of a constant number register 111 so as to output the result of multiplication as a CRO setting value 102 to the ere register 3.
Now, operation of the pulse width discriminating circuit shown in FIG. 1 will be explained.
First, a pulse width discrimination will be described on the case of decoding a pulse that has a variable period and that has been pulse modulated. The fact that the pulse has been pulse modulated, means that the input pulse has two different duty ratios. In the conventional example, it is assumed that, the input pulse assumes either a pulse form A-I (duty ratio of 30%) shown in FIG. 2 or a pulse form B-I (duty ratio of 60%) shown in FIG. 2.
For pulse width discrimination, whether the input pulse is the pulse form A-I or B-I can be discriminated by detecting the level of the input pulse during a period in which the pulse forms A-I and B-I take different levels from each other. In other words, the level of the input pulse is detected at any time point during a period of 30% to 60% of each period of the input pulse. If the detected level is a low level, it is discriminated that the input signal is the pulse form A-I, and if the detected level is a high level, it is discriminated that the input signal is the pulse form B-I. In the conventional example, the level of the input pulse is detected at a time point of 45%, which is an intermediate time point between a time point of 30% and a time point of 60%.
Now, this operation will be described with reference to FIG. 1 and FIG. 3 which is a timing chart illustrating an operation of the conventional pulse width discriminating circuit receiving the input signal composed of two pulse forms having different duty ratios.
When a pulse is applied to the input terminal 7 and the input signal 13 changes from the low level to the high level, the edge detecting circuit 13 outputs the edge detection signal 14. In response to this edge detection signal 14, the count value 9 of the counter 1 having counted up in response to the count clock f 8 is stored in the CPT register 2, and the counter 1 is cleared. The value (nl) stored in the CPT register 2 indicates one period of the input signal 13, and a time point of 45% in one period is set by using the value (n1) stored in the CPT register 2.
First, the arithmetic operation circuit fetches the value 101 stored in the CPT register 2, and multiplies the stored value 101 by the value of the constant number register I 11. In this case, 0.45 is previously set in the constant number register 111. The result of the multiplication is stored in the CRO register 3 as the CRO setting value 102. Thus, the value corresponding to 45% of one period is set in the CRO register 3.
On the other hand, the count clock f 8 is counted in the cleared counter I in a next period, and when the count value 9 becomes coincident with the CRO stored value 10, the comparator 4 outputs the coincidence signal 11, so that the latch circuit 6 latches the level of the input signal 13. Thus, the latch circuit 6 latches the level at the time point of 45% of one period of the input signal 13. Namely, the latched data 12 indicates the level at the time point of 45% of one period of the input signal 13. If the latched data is at a low level, the latched input signal is in the pulse form A-I, and if the latched data is at a high level, the latched input signal is in the pulse form B-I.
Incidentally, if the period of the input pulse is at a constant, the value set in the CRO register 3 my be fixed. However, if the period of the input pulse is variable, it is necessary to rewrite the CRO register 3 when the period of the input pulse varies. The conventional example is such that the period of the input pulse received before one period is measured, so as to estimate or approximate the period of the input pulse currently received.
Next, the pulse width discrimination will be described on the case of decoding the input signal that has been double pulse-modulated.
In this case, the input pulse assumes four pulse forms A-I, A-II, B-I, B-II shown in FIG. 2. The fact that the input signal has been double pulse-modulated, means that the pulse of one period indicates two bits of dam. In other words, a pulse indicative of data A is modulated by data I or date II. Specifically, if the pulse indicative of dam A is modulated by data I, the duty ratio of the dam A is maintained as it is, and if the pulse indicative of data A is modulated by data II, the duty ratio of the data A is changed to increase by 5%. In addition, a pulse indicative of data B is modulated by data I or date II. Specifically, if the pulse indicative of data B is modulated by data I, the duty ratio of the data B is maintained as it is, and if the pulse indicative of data B is modulated by data II, the duty milo of the data B is changed to increase by 5%.
In order to discriminate the pulse as mentioned above, it is sufficient if the level is detected at a time point X between 30% and 35% of one pulse period, at a time point Y between 35% and 60% of one pulse period, and at a time point Z between 60% and 65% of one pulse period. For example, if the level on the time point X is at a high level and the level on the time points Y and Z is at the low level, the pulse received at this time means the data A and the data II.
In operation, the rising edge of the input signal 13 is detected in the edge detecting circuit 5, and the count 9 (n1) is stored in the CPT register 2. Thereafter, the arithmetic operation circuit 100 performs a multiplication expressed by the following equation (1), and the result of the multiplication is stored in the CRO register 3 for level detection at the time point X. After the level detection at the time point X has been completed, the value of the constant number register 111 is rewritten to a value Y. Furthermore, the arithmetic operation circuit 100 performs a second multiplication expressed by the following equation (2) and the result of the multiplication is stored in the CRO register 3 for level detection at the time point Y. After the level detection at the time point Y has been completed, the value of the constant number register 111 is rewritten to a value Z. Furthermore, the arithmetic operation circuit 100 performs a third multiplication expressed by the following equation (3) and the result of the multiplication is stored in the CRO register 3 for level detection at the time point Z. Thus, the input pulse width discrimination is performed on the basis of the levels detected at the three different time points. EQU {CPR stored value 101 (n1)}.times.X (1) EQU {CPR stored value 101 (n1)}.times.Y (2) EQU {CPR stored value 101 (n1)}.times.Z (3)
Accordingly, the level detection is performed three times in each one period of the pulse.
As seen from the above, in the case of decoding the double-pulse-modulated signal the conventional pulse width discrimination circuit has to perform the multiplication operation a plurality of times. However, in a time required for a series processing for setting the CRO register 3, the proportion of time for the multiplication operation is greatly high and reaches about 50%. Accordingly, the plurality of multiplication operations increase a lead for the arithmetic operation circuit 10. In ordinary cases, the arithmetic operation circuit 10 is rarely provided exclusively for the pulse width discrimination circuit, and actually, the arithmetic operation circuit 10 is used not only for the pulse width discrimination but also for other various arithmetic operations (for example, as in a CPU of a microcomputer internally containing the pulse width discrimination circuit). In this case, the increase of the lead on the arithmetic operation circuit 10 results in a drop of the overall processing efficiency of the system.
In addition, since the rewriting of the set value of the CRO register 3 must be performed after the level detection at a detection time point has been completed, if a substantial time is entailed to set a value in the CRO register 3, when the pulse period becomes short, there is a fear that the setting of the CRO register becomes out of time. For example, it may be expected that, after the level detection on the time point X has been completed, the time point Y of the pulse passes before the equation (2) is executed to set the result of the multiplication to the CRO register 3. In this situation, a correct pulse width discrimination cannot be performed. Furthermore, if a substantial time is entailed to set a value in the CRO register 3, it becomes impossible to normally perform the pulse width discrimination in the case that a difference in duty ratio of input pulses is small.
For example, an index search of a VTR (video tape recorder) is performed to discriminate a duty ratio of a CTL signal stored in a longitudinal direction of a tape. In a search mode, pulse of the number near to about 6000 are inputted per one second. Therefore, if the level detection is performed three times for each one period Of pulse, the level detection must be performed 18,000 times per one second.
Here, considering the above mentioned pulse width discrimination in which the first level detection is performed at a time point of 30% of one pulse period and the second level detection is performed at a time point of 45% of one pulse period, since one pulse period is about 167 .mu.s, the value of the CRO register 3 must be rewritten during a time of 15% of one pulse period, namely, during a time length of 25 .mu.s. Since the time required for the rewriting is on the order of about 10 .mu.s, it is too small in margin.
In addition to this too small margin, since the arithmetic operation circuit 10 is not provided exclusively for the pulse width discrimination circuit, the generation of the set value for the CRO register 3 is left in a waiting condition when another processing is under execution.
As seen from the above, it is very difficult to rewrite the CRO register three times per one pulse period, in a time before the respective level detections, and there is a fear of a malfunction.